library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
ENTITY shift_reg4 IS
PORT (
D : IN std_logic_vector( 3 downto 0);
Q : OUT std_logic_vector( 3 downto 0);
SI: IN std_logic;
SO: OUT std_logic;
K : IN std_logic_vector (1 downto 0);
CLK : IN std_logic
);
END shift_reg4;
ARCHITECTURE behavioral OF shift_reg4 IS
SIGNAL data,data2 : std_logic_vector (3 downto 0);
SIGNAL inpt : std_logic;
BEGIN
data <= D;
inpt <= SI;
PROCESS (CLK)
BEGIN
IF (CLK'EVENT AND CLK = '1') THEN
IF ( K = "00") THEN
Q <= "0000";
ELSIF (K = "01") THEN
SO <= D(3) ;
Q <= data(2 downto 0) & SI ;
ELSIF (K = "10") THEN
SO <= data(0);
data <= SI & data( 3 downto 1);
ELSIF (K = "11") THEN
Q <= D;
END IF;
END IF;
END PROCESS;
END behavioral;