You have a "subthreshold slope", mV per decade of current.
Processes with less total working voltage, want to push VT
lower so drive current { (Vgs-VT)^2 } is maximized for speed.
The counter-effect is leakage.
Say it's 150mV/decade, and your FET has a VT(1uA) of 0.5V.
That means at Vgs=0, you will have ideally a ~1nA per
transistor leakage. Now consider that processing and temperature
might put your VT(1uA) as low as 0.3V, and you're at 10nA
(only 2 decades down) per 1-square device.