cheenu2002
Junior Member level 2
Hi,
I have read in some articles that subthreshold leakage current is a major problem faced by designers in lower process nodes like 65nm and 45nm. I would like to understand the physics behind this phenomena.. Why does it increase with decrease in Vt? Can anyone give me an intuitive or mathematical answer....
Also, I would lile to know how this is handled by analog design engineers.
I have read in some articles that subthreshold leakage current is a major problem faced by designers in lower process nodes like 65nm and 45nm. I would like to understand the physics behind this phenomena.. Why does it increase with decrease in Vt? Can anyone give me an intuitive or mathematical answer....
Also, I would lile to know how this is handled by analog design engineers.