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Why does latchup parasitic model not include parasitic bjt between source and drain?

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May 29, 2011
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I am confused about the explanations for latchup and latchup prevention.

I have seen the cross section views such as shown from a google search. image_preview.jpg

Why is it that there is no parasitic npn or pnp shown between the source and drain of the nmos or pmos, respectively?

The reason I ask is this: consider the case where the Output is inadvertently pulled a diode drop below ground (assume input to inverter is at ground so NMOS is off). Therefore, the pn junction consisting of the p-substrate and the NMOS drain n+ region will turn on. Based on latchup explanations I've read or watched, the resulting base current due to this diode turn-on will result in an npn collector current in the PMOS nwell. If there is sufficient voltage drop across Rw in the nwell, the pnp is turned on and the positive feedback loop with sufficient betas is triggered.

However, why is there no parasitic npn structure considered due to the drain n+, psub, and source n+ (again, assume NMOS input is low and NMOS is off)? If we consider the source n+ as a collector and not as just another emitter as shown in the diagram, is it not possible that when the Output (drain n+) goes below the psub ground potential, some of the 'collector' current will flow into the source n+ and not towards the nwell? Is it due to the doping such that the effective beta of the lateral npn of the source-psub-drain is negligibly low?

I've also read that placing guard rings between the NMOS and PMOS will reduce the substrate Rs and n-well Rw which will reduce the possibility of triggering the parasitic transistors. In addition, it is said that a p+ guard ring between the NMOS and PMOS will kill the beta of the lateral npn (n+ drain, p-sub, n-well), perhaps due to increased likelihood of injected electrons being recombined due to the p+. Is there a rough, quantitative figure we can relate to this lowering of lateral npn beta? For example, assuming fixed distance between an NMOS and PMOS, how much does the beta change when a p+ guard ring is added between them? 10x lower? 100x lower?

Thank you so much for your insights.
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