why does DC generate DEALY cell in netlist?

[quan228228]

Hi, guys

When i synthesis a module, the generated netlist has some delay cells. why?

In scripts, i dont set fix hold command. Any other command or other will enforce DC to generate delay cells?

Thanks!

David

Flowing are my synthsis scripts:
include ../artisan.scr /*this is used to read lib*/

mDESIGN = regfile

read -format verilog ../hdl/regfile/regfile.v

current_design = mDESIGN
create_clock -name clk -period 33 find(port,"clock")
set_clock_skew -plus_uncertainty 0.2 clk
set_max_fanout 8 current_design

set_operating_conditions WORST
auto_wire_load_selection = "true"
set_max_transition 0.5 current_design
set_max_capacitance 25 current_design
set_fix_multiple_port_nets -all -buffer_constants

link
uniquify
check_design

set_dont_touch_network find(port,"clock")
set_dont_touch_network find(port,"rstn")
set_dont_touch find(net,"rstn")
set_ideal_net find(net,"rstn")
set_false_path -from rstn
input_ports = all_inputs() - find(port, "clock") - find(port, "rstn")
set_input_delay 16.0 -max -clock clk input_ports
set_output_delay 16.0 -max -clock clk all_outputs()

compile_map_for_area = "true"
compile_sequential_area_recovery = "true"
set_prefer find (cell gsmc18_d0_ss/*1X)

compile -map_effort high

report_resources
report_clock
report_path_group
report_timing > ./report/rt.rpt
report_timing -nets -nworst 5 -max_paths 3 > ./report/rt2.rpt
report_timing -delay min > ./report/rt_hold.rpt
report_area > ./report/ra.rpt
report_cell > ./report/rc.rpt
report_hierarchy
report_design

report_constraint -all_violators -verbose > ./report/rv.rpt
write -f db -hie -o ./netlist/regfile + ".db"
write -f verilog -hie -o ./netlist/regfile + ".v"
quit

 

[sam536]

Check RTL too..Does your RTL have any Delay componets instantiation..
Some times DC will pick delay cells if your clock frequency is low.

If you dont need these cells, use set_dont_use on the initial runs before you put set_fix_hold. ....

Let us know if you find any other cause,..

Regards,
Sam

 

[quan228228]

Some times DC will pick delay cells if your clock frequency is low.

Regards,
Sam

Why?

David

Added after 47 minutes:

Could anyone explaint this issue from DC algorithm aspect?

thanks!

David