Why does the a=a+b expression that works in CPP not work the same CPP in Verilog???
when I used a=a+b; the expression, the last value of areg is not summed with b, the result return b not a+b in Verilog...
How can implement a=a+b with at least resource in FPGA
I guess it does work, but ..... verilog code is processed in parallel where the result is visible one clock later.
Verilog is not software that is processed line after line.
If you need more details, then
* show your code
* tell what you expect
* and what you see instead
Why does the a=a+b expression that works in CPP not work the same CPP in Verilog???
when I used a=a+b; the expression, the last value of areg is not summed with b, the result return b not a+b in Verilog...
How can implement a=a+b with at least resource in FPGA
module test_core
#(parameter WIDTH=16)
(input clk, input reset);
reg [15:0] a;
reg [15:0] b;
reg [15:0] k;
initial begin
a=0;
b=0;
k=0;
end
always @(posedge clk) begin
for (k = 0; k < 5; k = k + 1)
{
b=i;
a=a+b;
$display("-------Clock is triggerted...%0d ----",a);
}
end
endmodule //
In Verilog test bench print a reg value according to below:
Code:
-------Clock is triggerted...0 ----
-------Clock is triggerted...1 ----
-------Clock is triggerted...2 ----
-------Clock is triggerted...3 ----
-------Clock is triggerted...4 ----
But I expect this result:
Code:
-------Clock is triggerted...0 ----
-------Clock is triggerted...1 ----
-------Clock is triggerted...3 ----
-------Clock is triggerted...6 ----
-------Clock is triggerted...10 ----