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Why do we need to check the hold violations before setup?

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shelkerahul

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why is hold check done for the same edge

Hi all,


Why do we need to check the hold violations on one cycle before the setup.
eg. If I am checking the setup on 2nd cycle then I need to check the hold on 1st cycle, why it is so.

somebody help me, I am bit confuse in this.

Thanks in advance
 

spauls

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Re: Help on hold check

Hello shelkerahul,
Your path is multi cycle path , so hold is required one cycle before set up.
 

jarodz

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Re: Help on hold check

You can think hold/setup time in another way as min/max data path delay.
In multi-cycle path, when the data path delay too short, you will capture the data when it is in transition(hold time violation). The wrong way to fix the problem is to more shorten the delay of data path, then there is no hold time violation. But the timing will be wrong, the data will apear at the preceding cycle that you desire.
Therefore, the delay of data path must be in a rang, not too short or too long.


Regards,
Jarod
 

marksile

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Re: Help on hold check

Yes. I agree jarodz's viewpoint.
We must analyse setup/hold time in IC design.
 

Raptor

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Re: Help on hold check

Hold Check is performed one cycle before the setup (in single cycle) because :

1.In setup you check if data will be captured correctly in the next clock edge.
That is the data arrival time is before the data required time.Which in other words
means the data will not toggle in the setup window.
2. In hold check , you insure that the data launched will not corrupt the data being
captured at the same edge. That is the the data arrival time is after the hold window.

Eg: see attached bmp.

=> Data Launched by edge 1 by CLK1 will be captured by
edge 3 of CLK2.(setup check)
=> Also, at this point of time,EDGE 1 of CLK2 is
capturing the data from the previous EDGE 0 of CLK1.
(Not shown in figure but imagine or go back in time).
=> Now, if the path delay from CLK1 is very small then
data being launched by EDGE1 of CLK1(which is considered for setup)
will change in hold window of CLK2 and hence will corrupt data being captured(EDGE 0 of CLK1).

This is why hold check is done one cycle b4 setup.

Its lil difficult to explain. I hope this clarifies your doubt.
 
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