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[SOLVED] Why do we fix set up violations in pre CTS stage and hold violations after post CTS?

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biju4u90

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Why do we fix set up violations in pre CTS stage and hold violations after CTS?

Why do we fix set up violations in pre CTS stage and hold violations after CTS?
 

sharath666

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Setup violations are sometimes fixed by making changes to the logic. This can only be done preCTS. Hold violations are fixed by adding buffers to the data path. This is usually done postCTS. CTS itself leads to many hold violations.
 

biju4u90

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Changes in logic may fix hold violations too, right?
Suppose we have hold violations prior to the CTS stage itself. Then when should we try to fix it? After CTS or before CTS?
 

sharath666

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Logic changes cannot fix hold violations.(But logic changes can solve setup violations e.g. pipelining..)
You will get a true status of hold results only after CTS. So it is better we complete CTS and then look at hold results.
 

kannanunni

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Logic changes cannot fix hold violations.(But logic changes can solve setup violations e.g. pipelining..)
You will get a true status of hold results only after CTS. So it is better we complete CTS and then look at hold results.
but there is chances for postCTS hold fix to violate setup, right?
what we do for such situation?
 

sharath666

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Usually we never come across such a situation. But we may use different cells to overcome it.
 

biju4u90

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@sharath: I didn't get why logic changes cannot fix hold violations, but set up violations!! Can you explain in detail please?

The set up time equation is expressed as
Tclk>Tcq+Tcomb+Tsetup+Tskew

whereas the hold time equation is expressed as
Thold+Tskew<Tcq+Tcomb

So, if logic changes make any effect on set up time, it should make some effect on hold time too, right??
 

sharath666

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Ok. Assume u have setup violations in your design. You have to resolve it by reducing Tcomb. So 2 options available to u are pipelining and say retiming. Pipelining involves logic changes where you add registers to your RTL (logic changes)
Asume Tskew is 0 for simplicity..
If you have hold violations it means you have to push your data further ahead. You can do that by increasing TComb. The easiest way to do that is to add buffers in the data path. With this you can get incremental and precise control over the delay. If you want to do logic changes to solve this problem, what logic will you add in the data path. Any logic changes proposed will only complicate your problems.
 

biju4u90

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That was a wonderful explanation. Thanks Sharath. :)
 

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