hi,
you know what CTS does.. it inserts clock buffers and forms a clock tree such that clock skew from source to all flipflops are same..
If you design is not meeting setup time constraints then additional buffers leads to more complicated violations and similarly for hold violations.. if we have setup violations then this delay in clock path can also correct that violations..
since set time violations are w.r.t max propogation delay and hold time violations are w.r.t min propogation delay , when buffers are inserted based on setup violations in CTS, it will mostly(not always) try to reduce hold violations too. but still there are quite a few exceptions cases where , there could be hold violation even after CTS, thus we deal them seperately after CTS.