Why do we define set up and hold time?

[ASIC_intl]

Why do we define set up and hold time? Why are they needed to be defined?

 

[gilbertomaldito]

set up and hold

set-up and hold time are the safest margin your clock signal should sample data as i guessed you've already knew. They are needed to be defined because you have to make sure your clock samples the data at its (data) most stable state. These margins should also be defined due to jitters on both clock and signal.

 

[ASIC_intl]

Re: set up and hold

Hi

I want a more clear explanation of it showing interms of delay etc. DO U HAVE ANY DOCUMENT THAT CLEARLY AND BEATIFULLY EXPLAIN IT?

 

[cheelgo]

set up and hold

mostly is to avoid data metastability in brief!

 

[gilbertomaldito]

set up and hold

hi, you can refer to this link:
**broken link removed**

hope this helps.

 

[ljxpjpjljx]

Re: set up and hold

because we need to aviod the meta state!

 

[ASIC_intl]

Re: set up and hold

hi andrew_matiga

the above document wries about two flops and their timing. it does not say about calculating set up time for a single flip flop. do u know any document that writes about setup/hold time for a single flipflop?

 

[Jifeng.Cui]

set up and hold

If you want to calculating setup/hold delay of single flipflop, you can refer to the defination, so you can get it. Simply to say, the delay are defined as below: the data must arrived early than clk, when you moved the data towards the clk, the cell delay (Tdq) would keep stable unless you move the data too closer, then the cell delay would rise. The setup delay is defined as the Tdq rise to 1.1X, or 10% higher. so as hold...

 

[ASIC_intl]

Re: set up and hold

HI Jifeng.Cui

I want a document which describes what you have more reudimentarily and more clearly. Do u know any book or document where it can be found?