Whenever latch is enabled it will pass watever is there on its D inputs to Q output. If suppose any glitch is coming on D and latched is enabled it will pass it to q. Glitch always create problem u would be knowing this.
Latches are fast,consumes less power, less area than Flops but Glitches can also come along with this advantages.Thats why we for flops.
latch is not good ,since STA is based on posedge of clk to do timing check and latch is level sensitive. also DFT need to do some special step to tackle this latch!
Latches will allow the data at the input to reflect at the output till the entire time the Latch is enabled , ie when it is enabled it is called to be transparent ie the output follows the input thus if a glitch appears it will be reflected at the output
but the case with FF is not so , the output follows the input only at the edge of the clock whether positive or negative .
thus any glitch appearing at the input will not be transfered to the output unless the clock edge appears
Tauqueer,
If your design is complety latch based design( usuallly IBM designs) then you can use the LSSD scan else normal scan FF based desing, you can make the latches as transparent during testmode. For example clock gating cells has the latch, you ORed with testmode signal.
non transparent latches are modeled as TIEX by the ATPG tool. So the coverage drops.
~C Santhosh Kumar
Before enable of the Latch place a 2X1 mux with sel and one pin tied with test mode signal (OR gate with testmode and actual enable signal). Intent is to make Latch always on while doing DFT coverage..