Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Why do I get glitches when I simulate this program?

Status
Not open for further replies.

kumar_eee

Advanced Member level 3
Joined
Sep 22, 2004
Messages
814
Helped
139
Reputation
276
Reaction score
111
Trophy points
1,323
Location
Bangalore,India
Activity points
4,676
When I simulatiing the following prgrm,Why the glitches are coming in the output?..

module test(clk,a);
input clk;
output a;

reg a;

always @ ( clk )
begin
a=0;
a<=1;
$display(a);
end
endmodule
 

echo47

Advanced Member level 5
Joined
Apr 7, 2002
Messages
3,942
Helped
637
Reputation
1,272
Reaction score
88
Trophy points
1,328
Location
USA
Activity points
33,178
glitch

You should not see glitches in the text display. You should see a continuous stream of "0" values with no "1" values.

Each time a "clk" transition occurs, "a=0" immediately drives "a" low. "a<=1" schedules a go-high event to be executed after all active events complete. Since "$display(a)" is an active event, "a<=1" will update "a" after the "$display(a)". That's why you shouldn't see any "1" messages in the text output.

If you are looking at a waveform display in a GUI simulator such as ModelSim, it shows you a plot of the continuous value of "a" irregardless of $display statements. You will see "a" high most of the time, but glitching low briefly after every "clk" transition.

By the way, it's usually a bad idea to mix blocking and nonblocking assignments in the same "always" block.
 

Status
Not open for further replies.

Similar threads

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top