kumar_eee
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When I simulatiing the following prgrm,Why the glitches are coming in the output?..
module test(clk,a);
input clk;
output a;
reg a;
always @ ( clk )
begin
a=0;
a<=1;
$display(a);
end
endmodule
module test(clk,a);
input clk;
output a;
reg a;
always @ ( clk )
begin
a=0;
a<=1;
$display(a);
end
endmodule