Why do/did people use latches in digital circuit design, ASICs in particular

[matrixofdynamism]

Latches have existed for probably as long as flip flops as building blocks of digital circuits. However, they make timing analysis harder and thus are to be avoided.

As far as I understand there are cases in which latches are still used in ASIC design instead of flip flops. Why should anyone use latches? Why is their support not completely removed from digital circuit design-implementation tool suite so people may only use flip flops?

 

[TrickyDicky]

If I understand, its can be a power thing.
With a clock constantly switching, you're always using power. With a latch the big power draw is only on the switch, so the power draw is less.

Also, they can be used in situations where you have no clock.

 

[std_match]

Latches are needed for some special functions. One example is glitch-free switching between two asynchronous clocks.

Edit:
The example is not correct. No latch is needed for glitch-free clock switching:
https://www.eetimes.com/document.asp?doc_id=1202359

 

[K-J]

Latches have existed for probably as long as flip flops as building blocks of digital circuits. However, they make timing analysis harder and thus are to be avoided.

As far as I understand there are cases in which latches are still used in ASIC design instead of flip flops. Why should anyone use latches? Why is their support not completely removed from digital circuit design-implementation tool suite so people may only use flip flops?

Latches take less silicon area and use less power than a flip flop. Go back to the basics and study the design of how a flip flop is constructed from a latch.

The fact that latches are discouraged in FPGA designs is simply because FPGAs have actual hard flip flops designed into the silicon, they typically do not have hard latches. The reason FPGA suppliers choose to put actual flip flops but not actual latches in their silicon is a business decision based on how they want to market their product to appeal to a large customer base. It is not a technical decision.

Kevin Jennings

 

[matrixofdynamism]

"glitch-free switching between two asynchronous clocks.", how?

I thought the reason why people are told not to use latches is because they make timing analysis hard. I have never been taught of any situation in which we would actually need to use latches and have always been told to avoid them.

 

[std_match]

"glitch-free switching between two asynchronous clocks.", how?

I am sorry, it is not a correct example. No latch is needed to do glitch-free clock switching.

As already mentioned in the thread, latches can be useful for low-power design when you don't want to have a clock running.

 

[sharath666]

Hi KJ. Are you sure latches are not provided by FPGA suppliers. I remember components like LPDCE (which are latches) when I was working on FPGAs around 5 years back.

 

[TrickyDicky]

They may have provided the component primitives libraries that may have historically provided latches, but the silicone doesnt have them. They will get emulated with Luts.

Afaik, no FPGA going back to the mid 90s (Ive worked with flex10ks) has latches - they are all made with luts and registers.

The reg in the slice/alut may have some async pre-set or reset pins it may use to emulate the latches.

 

[ads-ee]

Afaik, no FPGA going back to the mid 90s (Ive worked with flex10ks) has latches - they are all made with luts and registers.
The reg in the slice/alut may have some async pre-set or reset pins it may use to emulate the latches.

Well if you go back further circa 1988-89...back when the original XC3000 series parts were introduced they do have actual latches. The input storage element in the I/O could be configured as either latches or flip-flops. You can look for latch in the following document. **broken link removed**

I also vaguely recall that the XC2000 series parts actually had CLB latches, only worked with one design that had that part.
Well I just checked and it did have latches...http://pdf.datasheetcatalog.com/datasheets/restul/374736_DS.pdf page 2-190 describes the CLB storage element.

I'm pretty sure when Xilinx produced the 4000 series they completely dropped support for latches.

Regards

 

[matrixofdynamism]

So what this boils down to is that latches are required in low power design, and that is it.