irun2
Member level 2
Hi everyone!
When I tried to import a synthesized verilog netlist containing the assign statements, like assign out = (reset==1'b1)? 8'b0: (result | temp);
Cadence has used some symbol "cds_thru" connected to the out port, LVS failed due to these devices Layout view didn't have...
What should I do to make LVS pass? Do I have to write the RTL then recompile? That's a huge work to do...
When I tried to import a synthesized verilog netlist containing the assign statements, like assign out = (reset==1'b1)? 8'b0: (result | temp);
Cadence has used some symbol "cds_thru" connected to the out port, LVS failed due to these devices Layout view didn't have...
What should I do to make LVS pass? Do I have to write the RTL then recompile? That's a huge work to do...