Chinix
Newbie level 5
I create a module then synthesize it.Everything goes well.
But when I call it in upper block,my synthesis tool tell me there is some logic cannot be synthesized.
I do all my work in ISE6.3i.
Why does this happen?
And how should I deal with it
thx
But when I call it in upper block,my synthesis tool tell me there is some logic cannot be synthesized.
I do all my work in ISE6.3i.
Why does this happen?
And how should I deal with it
thx