Why cann't my unit be synthesized in top level

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Chinix

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I create a module then synthesize it.Everything goes well.
But when I call it in upper block,my synthesis tool tell me there is some logic cannot be synthesized.
I do all my work in ISE6.3i.
Why does this happen?
And how should I deal with it
thx
 

Could you give us more info or sample of your code if it's not big?
 

do u want to tell that ur independent modules are correctly getting synthesised. but when u integrate it, itz giving problems?

whatz the exact error itz giving?

plz try to detail the problem.
 

yeah
i write a frequency division module(name it "pre_freq_div") in order to output different frequency related to the division coefficient input,and the coefficient may be large（14-bit）.
this module get synthesized correctly independently. i also simulate it in modelsim se 6.0, the wave is perfect, i think.
But when this module is getting into use from top level design,the systhesis tool tell me:
Synthesizing Unit <pre_freq_div>.
Related source file is pre_freq_div.v.
Register <counter> equivalent to <freq_out> has been removed
ERROR:Xst:739 - Failed to synthesize logic for signal <freq_out>.
ERROR:Xst:1431 - Failed to synthesize unit <pre_freq_div>.
 

Can you post ur code for pre_freq_div.v here... if you dont mind!
 

Here is my freq div module below.
I wish it does not make too much trobule


module pre_freq_div(clk,_reset,div_coef,freq_out);
input clk,_reset;
input [13:0] div_coef;
output freq_out;
reg freq_out;
reg [13:0] counter;

always @ (posedge clk)
begin
if(_reset==0)
begin
freq_out=0;
counter=0;
end
else
begin
if(div_coef==14'b0) freq_out=0;
else
begin
if(counter!=div_coef)
begin
counter=counter+1;
freq_out=freq_out;
end
else
begin
counter=0;
freq_out=~freq_out;
end
end
end
end

endmodule
 

everything looks ok.. cept of the _reset thing.. im not sure if thats valid or not.. cause i never use that naming style.. (perfer rst_n)..

i don't have anything installed to compile/synth it.. to see what it says.. but i cleaned it up to how i would format it.. try it and see if that makes a difference.. if so it could just be syntax..

im assuming your instantiating that module.. so it could be something on the next module up..

jelydonut
 

Here I have modified ur code aq little bit. Hope you were not using
freq_out as clk for other modules. I changed this signal to single clock
pulses, use this one as clk enable in other modules!
Hope this sloves ur problem.

Code: 
module pre_freq_div(clk,
                    reset_n,
                    div_coef,
                    freq_out);
   input clk, reset_n;
   input [13:0] div_coef;
   output      freq_out;
   reg         freq_out;
   reg [13:0]  counter;
   
   always @ (posedge clk) begin
      if (!reset_n) begin
         freq_out <= 1'b0;
         counter  <= 0;
      end else begin
         if (div_coef == 14'b0)
           freq_out <= 1'b0;
         else begin
            if (counter == div_coef) begin
               counter <= 0;
               freq_out <= 1'b1;
            end else begin
               freq_out <= 1'b0;
               counter <= counter+1;
            end
         end
      end
   end
endmodule // pre_freq_div
 

It is right!
You ought write your always procedure using the non-block assign (<=), Not using bl;ock assign (=).
 

visualart said:
It is right!
You ought write your always procedure using the non-block assign (<=), Not using bl;ock assign (=).
Click to expand...

this influences synthesis procedure so much?
 

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