matrixofdynamism
Advanced Member level 2
Race conditions can be prevented if the simulator determines the order of parallel events, why do they still occur?
Fundamentally, race conditions occur in simulation because the HDL or HVL code is fundamentally written to run in parallel via multiple processes (or always blocks in Verilog). However, in reality those parallel processes shall run in a sequence on a processor using multithreading. Therefore, it comes down to which of the many parallel processes in the testbench is executed first by the processor, it is impossible to say this with certainity and this uncertainity is nature of multithreaded programs. The actual behaviour for a given testbench however varies between simulators e.g in some simulators an verilog initial block may not necessarily run before other verilof always blocks, in other simulators the verilog initial block may always be run before the verilog always blocks. This makes race conditions elusive as they may not manifest on all simulators and all versions of the same simulator.
In my understanding, if the simulator determines which ALL events are to occur at time X in simulation from different parallel processes in advance, race conditions can be easily prevented. Why do simulators not do this? Since all processes ultimatly are part of the same simulation and connected to the same simulation time, why can the simulator tool not predict what events are expected to occur at what time and thus prevent race conditions?
Fundamentally, race conditions occur in simulation because the HDL or HVL code is fundamentally written to run in parallel via multiple processes (or always blocks in Verilog). However, in reality those parallel processes shall run in a sequence on a processor using multithreading. Therefore, it comes down to which of the many parallel processes in the testbench is executed first by the processor, it is impossible to say this with certainity and this uncertainity is nature of multithreaded programs. The actual behaviour for a given testbench however varies between simulators e.g in some simulators an verilog initial block may not necessarily run before other verilof always blocks, in other simulators the verilog initial block may always be run before the verilog always blocks. This makes race conditions elusive as they may not manifest on all simulators and all versions of the same simulator.
In my understanding, if the simulator determines which ALL events are to occur at time X in simulation from different parallel processes in advance, race conditions can be easily prevented. Why do simulators not do this? Since all processes ultimatly are part of the same simulation and connected to the same simulation time, why can the simulator tool not predict what events are expected to occur at what time and thus prevent race conditions?