Why are the lint check done ?

[hemant_rathee]

Can anyone help me about the lint checks. Why the lint checks are done. What are its advantages and disadvantages. Which are the lint tools used ?

 

[blooz]

Linting is basically Static Code analysis /Design Rules checker...


some of the lint tools

1.h**p://www.asic-world.com/verilog/tools.html

2.h**p://bawankule.com/verilogfaq/page4.html

Also the Higher end Simulation Tools Have LINT tools Integrated into them
Like Riviera Pro .Most often LINT tools can report Warnings which may be otherwise
not visible .Lint tools generally perform static analysis of source code.

//A simple Example

library ieee;
use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity tests is 
	port (a:in unsigned(7 downto 0):=x"06";
	b:in unsigned (7 downto 0):=x"06" ;
	c:out unsigned (7 downto 0));
end tests;


architecture tests of tests is 
--
--
	  function mult (a,b:in unsigned (7 downto 0) ) 
	return unsigned is 
	variable z:unsigned (15 downto 0):=X"0000";
	variable y:unsigned (15 downto 0);
	variable i:integer:=0;
	begin 	
		y(7 downto 0):=b;
		while(i<7)  loop 
		if(a(i)='1') then 
			z:=z xor y; 
			end if;
		y:= y(7 downto 0)*x"02" ;
		if (y(11 downto 0)>=X"100") then 
			y:=y xor X"111d";	
		end if;	
		  i:=i+1;
		end loop ;
	 return (z(7 downto 0) );
	end mult; 
begin 
	c<=mult(mult(a,b),a);
end tests ;

The above code compiles with zeros errors

but When Linting is Enabled Some Warnings could be found

like (my simulator is Active HDL )

# Compile Architecture "tests" of Entity "tests"
# Warning: LINT_3024: mul_Tests.vhd : (17, 1): Initial value is ignored by synthesis tool
# Warning: LINT_3024: mul_Tests.vhd : (19, 1): Initial value is ignored by synthesis tool
# Warning: LINT_2005: mul_Tests.vhd : (26, 1): Operator * (mul) used
# Compile success 0 Errors 4 Warnings  Analysis time :  1.0 [s]

ALINT is LInt tool from Aldec ...

Here is the Link with details on the tool ,

h**p://www.aldec.com/Products/Product.aspx?productid=47596ec7-3775-4c14-a874-e069790e648a

 

[poluekt]

Lint tools checks RTL code, helps to make the HDL design reusable, portable, synthesizable, and testable.
Checking properties:
naming conventions
file format
coding style
synthesizability
FSM
structural
DFT
clockdomain
scanchain

Tool example: cadence hal (included into ius)
Synopsys DC also perform linting checks, report may get with command check_design

Warning: In design 'top', input pin 't1_start' of hierarchical cell 'CLK_CTR' has one or more internal loads, but is not connected to any nets. 'Logic 0' is assumed. (LINT-59)