WHY AND/OR PLANES IN FPGA?

[Naz]

WHY WE HAVE AND/OR PLANES IN FPGA,WHY NOT NAND/NOR PLANES EVEN THOU THEY ARE CALLED UNIVERSAL GATES ?

 

[nand_gates]

You can have nand/nor planes in FPGA!!
But the reason why its not there is logic optimization and maping
will be difficult!!
But you can have nand/nand planes in FPGA!!!

 

[Naz]

IN XILINX WE HAVE AND/OR PLANE NOT NAND/NOR.NAND /NOR ARE CALLED UNIVERSAL GATES,CAN BE USED TO IMPLEMENT ANY GATE,ALL LOGIC FAMILIES (MOSTLY) IMPLEMENT INVERTED LOGICS OR OUTPUTS.
BUT MY QUESTION IS CONSIDER I KNOW NOTHING EXCEPT THAT NAND/NOR ARE UNIVERSAL GATES,IF THEY ARE DECALRED AS SO THEN WHY XILINX HAS NOT USED THESE GATES?THEY CAN AT TIMES OPTIMIZE THE DESIGN,ITS NOT THAT AND OR WILL OPTIMIZE DESIGN ONLY.IF ONE THING IS DECLARED AS UNIVERSAL THEN IT SHOULD BE USED IF NOT THEN THERE IS NO USE OF CALLING IT UNIVERSAL.

 

[Big Boy]

Hello

First, (not to be offensive) please do not post typing UPPERCASE words. Typing in UPPERCASE meen yelling in forums, and is harder to read. And, this is something that people doesn't like, especially moderators

Ok, well, it would be possible to use NAND/NOR plane. Yes, on a theorical base, NAND/NOR gates can be used to model any gates. However, in a complex design, if you would be to use solely NAND/NOR gates, this would work, but could be much slower, as more of those gates would be required.

Also, you have to note that inverters are probably the most common resources in FPGA. It doesn't look much, but if you take a look with an FPGA editor tool, you will see that at almost every gates or flip-flop, you have a multiplexor at output, which you have the choice to select inverted or non-inverted result.

So, especially for synthesis tools, it is much easier to synthesize the design with non-inverted gates, and if invertion is required, use the provided inverters in FPGA.

The gates are universal in the sense that the output can be inverted if needed.

Note also that most gate logic, in FPGA, are coded in a programable ROM-like structure, which set a single bit output according to several input. This make decoding of expressions much faster, and predictable. Those are called look-up tables (LUT).

 

[Naz]

All needed logical equations (equivalently, combinational circuits) can be constructed using the three logical operators (gates): and, or and not. Because of DeMorgan's laws, we only need either and and not, or (or and not) to form a complete logic. These same results can also be accomplished using a different (but related) set of operators: nand and nor.

nand == not (and)

nor == not(or)

This approach is used in FPGA,De Morgan's Law
as this is the bases of declaring Nand /Nor as UNIVERSAL GATES.

 

[echo47]

You guys are talking very strange things! When I design with FPGAs, I don't think about gates or DeMorgan rules. I think about higher-level functions such as counters and adders and state machines. I let the HDL compiler map my logic into the FPGA's internal architecture. Besides, an FPGA is not a sea-of-gates, it is a sea-of lookup-tables (and flip-flops and other things). Try downloading a Xilinx user manual and look at what's inside each configurable logic block.

 

[Jackwang]

This is structure problem.
i think it is sample and easy to implement in hardware.