WHy always 4:1 MUX or 1:4 DEMUX in CDR?

[raymond_luo2003]

demux architecture used in cdr

Dear all,

There seems almost every high speed SerDes got 8B/10B encoder in high speed link or optical link, so the parallel data got the 10 bit buswidth. I just wander why there is no particular paper mentioning about the 10-phase sub-rate phase detector instead of 2^n sub-rate phase detector? It really put me in puzzle.

Why not adopt the 5:1 MUX ( or 10:1 MUX) and 1:5 DEMUX( or 1:10 DEMUX) directly? It should be more natual, right? Anyone have relevant paper regarding on the non-2^n type MUX/DEMUX or CDR?

Anyone got any idea?

 

[rficlover]

it may because that the protocol always increase the data speed by 4 times

 

[ljw108]

Although too many days were passed, I just write my opinion.
I also wonder about same problem recently.
Just my thinking, 2^n comes from the tree architecture and using up&down edges.
Specifically, Even number comes from two edges and exponential factor comes from tree architecture.