subramanyam said:Hii Friends ,
Why we need 50% duty cycle clocks ?? Can't we use some other duty cycle value ?? What are the advantages of using 50% duty cycle waveform ?
thanx,
subbu.
Tan said:But how can we use negedge and posgede in the same programm,(in vhdl not verilog)
and i always use default clockin my program.never evr changed the duty cycle..
can anybody explain me why we have to change the duty cycle and in which instances we have to chnage the duty cycle.
Why we need 50% duty cycle clocks ?? Can't we use some other duty cycle value ?? What are the advantages of using 50% duty cycle waveform ?
Let us say my design is not a latch based design and I am goin to use only one edge either +ve or -ve. In this case , Can I use any other duty cycle clock ?
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