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why 50% duty cycle is needed ?

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subramanyam

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Hii Friends ,

Why we need 50% duty cycle clocks ?? Can't we use some other duty cycle value ?? What are the advantages of using 50% duty cycle waveform ?

thanx,
subbu.
 

nandhika

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hi
u can use other than 50% also but hardware is less for designing 50% clock cycle so everyone prefer 50%clock cycle.
 

rjainv

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1) if you are using negedge flops, then dutycycle matters
2) if you have latches, dutycycle matters
3) there were more reasons... I am trying to recall..
 

asicengineer1

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how about latching data on both edges of clock cycle like in DDR ? i think there was a similar post sometime back.
 

atuo

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subramanyam said:
Hii Friends ,

Why we need 50% duty cycle clocks ?? Can't we use some other duty cycle value ?? What are the advantages of using 50% duty cycle waveform ?

thanx,
subbu.

Hi subbu,

If you logic use both posedge and negedge of clk, the 50% duty cycle is need.

Thanks
 

Tan

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But how can we use negedge and posgede in the same programm,(in vhdl not verilog)

and i always use default clockin my program.never evr changed the duty cycle..
can anybody explain me why we have to change the duty cycle and in which instances we have to chnage the duty cycle.
 

rjainv

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Tan said:
But how can we use negedge and posgede in the same programm,(in vhdl not verilog)

and i always use default clockin my program.never evr changed the duty cycle..
can anybody explain me why we have to change the duty cycle and in which instances we have to chnage the duty cycle.

What if you had back to back latches... or in other words a data pipeline made of latches ? then you need to have non-overlapping clocks for alternate stages....
 

tarmember

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The 50% duty cycle has also relationship with the power. If you have a 50 % duty cycle then less power is consumed by clock generator then that of the consumed by lesser/higher duty cycle.(this is related to Fourier transform of square wave).
Hope this helps you....

Regards,
Tarang
 

avantika10

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could anyone tell me how the hardware will be inferred if data is captured on both edges of the clock cycle ?
 

sameer_dlh25

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Why we need 50% duty cycle clocks ?? Can't we use some other duty cycle value ?? What are the advantages of using 50% duty cycle waveform ?

In any design if you are using both the edges of the clocks or both the levels of the clocks then 50 % duty cycle is important to ensure easy timing sign off. such scenario includes

1. Latch based design with both the phases of clock are used.
2. When in a design both posedge and negedge are there.

:D
 

subramanyam

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Hii, thanx for the response !!!

Let us say my design is not a latch based design and I am goin to use only one edge either +ve or -ve. In this case , Can I use any other duty cycle clock ? I can definetely use, but whether, are there any conditions which we have to consider for how much duty cycle we have to take ??

If there are problems in not using a 50% duty cycle like NANDHIKA's more hardware statement and TARANG'S more power consumption statements plz strengthen these statements by furthur discussions and plz attach the related documents .

Best regards,
subbu.

Added after 20 minutes:

could anyone tell me how the hardware will be inferred if data is captured on both edges of the clock cycle ?

Hi Avanthika,

Definately there will be two types of flip flops inferred , few will be operating with posedge and others will be with the neg edge !!! Now the outputs of these two different edge flops will be driven onto the same data output , so that u can get ur data output on both edges of the clock.

regards,
subbu.
 

sameer_dlh25

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Hi Subbu,

Let us say my design is not a latch based design and I am goin to use only one edge either +ve or -ve. In this case , Can I use any other duty cycle clock ?

One more case I can think of if your clock is fed to any hard block such as RAM or ROM then they usually demands for 50% duty cycle. This is again because of their internal logic style. But this is not always the case.

Tarang ,
Could you please elaborate how duty cycle imapct the power consumtion of the circuit ?
Point is not very clear
:|
 

nandhika

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hi mr.subramanyam...

sorry for late reply..........

as per my knowledge to design a 50% duty cycle clock is much easier and it can be implemented just with one flipflop......

i mean suppose u have 100mhz and u want to derive 50 mhz with 50% dutycycle..........

Added after 2 minutes:

hi,

same thing try for 75% duty cycle.........u can feel that u require some more gates to implement it..........

if am wrong any one can correct me..............
 

uditkumar1983

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Hi all,

Nandhika I am not satisfied with your statement (50% duty cycle clock is much easier) .
Suppose you want to double the frequency than for getting 50 % duty cycle you required PLL/DLL/DCM means its very difficult , but if you don't want 50% duty cycle than you can design it simply ........

But as I think in a big design both edges are being used , because some signal are having active low and some signal active high ( like interrupt signal mostly you will find active low) ....

Take one Example of data transfer from one block to another block (both are working at same clock):
Suppose 1st block is trasfering data at the any edge of clock (take +ve )than if you are not using 50% duty cycle as well as working on one edge than for satisfactory operation you need to wait upto next same edge for sampling that data .... but if you are using 50% duty cycle as well as working on one edge on 1st block and 2nd edge in 2nd block than you can sample that data at the next (-ve edge only) So you need to wait only for .5*Clock Period ..........and Hence your Speed of operation will increase ...........
So for Simplified design and getting high speed 50% duty cycle is used ........( mostly)

If I am wrong than notify me .......

Regards
 

nandhika

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hi udit....

i agree to u only when those two modules are independent....to each other

suppose if one module output is depending on other module there comes the synchronization problem......

i mean synchronising inputs or enables (if it is there)..


i think ........
 

uditkumar1983

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Hi Nandhika
I means for a big design like SOC , so there are a lot of modules ( in itself its a big design ), so there only few signal are trasferred between then , if there is synchronization problem then we can used synchronizer .........
Please continue the suggestion .
Happy weekend...
Regards ......
 

baonguyenpro

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Duty cycle is safe way to guarantee set-up time and hold-time of clock.
 

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