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Wht is Cycle Stealing

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spartanthewarrior

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Can any Body tell me what is cycle stealing

and how it's effect a design

and also can any body refer some docs related to it.
 

A.Anand Srinivasan

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cycle stealing is the usage of certain cycles of the clock for some processing while the system say a microprocessor is interfacing with a much slower device or peripheral...
 

sunjimmy

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In pipelined synchronous design, the combination logic inside every stage must be done within one clock cycle. What if there is one particular stage which path delay is larger than one clock cycle?

One method called clock stealing is that you can delay the clock to the specific FF which is the latched FF of that particular stage, then for this particular stage, the path delay can be larger than one clock cycle. BUT for the subsequent stage after that particular stage, its allowed path delay is shorten because you move the timing boundary intentionally between these 2 stages. You steal some time from its subsequent stage for that particular stage.

Hope it helps :)
 

gck

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Cycle stealing can be done when you can adjust with one more clock delay.
 

phutanesv

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Dear Dude,

Cyclic stealing is also called as Time borrowing where there is pipelining of logic blocks.

phutane
 

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