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In pipelined synchronous design, the combination logic inside every stage must be done within one clock cycle. What if there is one particular stage which path delay is larger than one clock cycle?
One method called clock stealing is that you can delay the clock to the specific FF which is the latched FF of that particular stage, then for this particular stage, the path delay can be larger than one clock cycle. BUT for the subsequent stage after that particular stage, its allowed path delay is shorten because you move the timing boundary intentionally between these 2 stages. You steal some time from its subsequent stage for that particular stage.