Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Who will decide the number of metal layers in block level?

Status
Not open for further replies.

udayalakshmi91

Newbie level 1
Joined
Oct 15, 2018
Messages
1
Helped
0
Reputation
0
Reaction score
0
Trophy points
1
Activity points
7
Who will decide number of metal layers in block level

Who will decide number of metal layers in block level and can we add metal layers if we want.
 

Re: Who will decide number of metal layers in block level

Who will decide number of metal layers in block level and can we add metal layers if we want.

The most senior engineer handling the top level will decide the metal stack, the power structure, and the implications for block level. As a block level designer, you can argue about the decision but you can't change it yourself.
 

Re: Who will decide number of metal layers in block level

This is a chest-bumping deal between the later users of the
cell library (who want maximum routing levels and minimum
blockages in the lower levels) and the folks who have to make
all 500 gate primitives laid out at maximum placement density.
The minimum is obviously 1 metal layer, easier if you allow poly
routes. More common is 2 layers (if you are in a technology
with 4 or more).


If you take ownership of the cell library then of course you
can do as you please. But that means becoming responsible
for recharacterizing and requalifying the cell library, which
by your question I think is not something you're prepared for.
 

Re: Who will decide number of metal layers in block level

This is a chest-bumping deal between the later users of the
cell library (who want maximum routing levels and minimum
blockages in the lower levels) and the folks who have to make
all 500 gate primitives laid out at maximum placement density.
The minimum is obviously 1 metal layer, easier if you allow poly
routes. More common is 2 layers (if you are in a technology
with 4 or more).


If you take ownership of the cell library then of course you
can do as you please. But that means becoming responsible
for recharacterizing and requalifying the cell library, which
by your question I think is not something you're prepared for.

I believe the OP is talking about blocks in a SoC, not standard cells.
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top