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Who can tell me what difference of them? (VHDL)

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75 sinfocia

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signal rd,dr : std_logic;
ad_bus,ram_bus : inout;
:cry:
1.
process(rd) ---- right.
begin
if (rd='0' and dr='1') then
ad_bus_out<=ram_bus;
else
ad_bus_out<="ZZZZZZZZ";
end if;
ad_bus<=ad_bus_out;
end process;

2.
process(rd) ---- error.
begin
if (rd='0') then
if dr='1' then
ad_bus_out<=ram_bus;
else
ad_bus_out<="ZZZZZZZZ";
end if;
end if;
ad_bus<=ad_bus_out;
end process;

3.
process(rd,dr) ---- right.
begin
if (rd='0') then
ad_bus_out<=ram_bus;
else
ad_bus_out<="ZZZZZZZZ";
end if;
ad_bus<=ad_bus_out;
end process;

4.
process(rd) ---- error.
begin
if (rd='0') then
ad_bus_out<=ram_bus;
else
ad_bus_out<="ZZZZZZZZ";
end if;
ad_bus<=ad_bus_out;
end process;
 

cuiyujie

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Hi,

It's not clear what's dr, ad_bus_out and what you really want to implement for those 2 signals. One thing you should keep in mind is to make the sensitivitly list complete in process if you want to use process.

Or else, Another way maybe just as simple as:
ad_bus <= ram_bus when rd = '0' else
"(others => 'Z');
 

wjhzhx

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The process 2 is wrong because it will generate latch, when rd = 1, what is the result ?
But I can't understand where is wrong in process 4
 

VicL

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75 sinfocia said:
signal rd,dr : std_logic;
ad_bus,ram_bus : inout;
:cry:
1.
process(rd) ---- right.
begin
if (rd='0' and dr='1') then
ad_bus_out<=ram_bus;
else
ad_bus_out<="ZZZZZZZZ";
end if;
ad_bus<=ad_bus_out;
end process;

2.
process(rd) ---- error.
begin
if (rd='0') then
if dr='1' then
ad_bus_out<=ram_bus;
else
ad_bus_out<="ZZZZZZZZ";
end if;
end if;
ad_bus<=ad_bus_out;
end process;

3.
process(rd,dr) ---- right.
begin
if (rd='0') then
ad_bus_out<=ram_bus;
else
ad_bus_out<="ZZZZZZZZ";
end if;
ad_bus<=ad_bus_out;
end process;

4.
process(rd) ---- error.
begin
if (rd='0') then
ad_bus_out<=ram_bus;
else
ad_bus_out<="ZZZZZZZZ";
end if;
ad_bus<=ad_bus_out;
end process;
May be you have conflict with other design part
when dr signal not used in examples 2 and 4?
 

linuxluo

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Hi,
I think first thing is to complete your sensitive list of your process ,otherwise you can't simulate it correctly.
 

corgan

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All of four blocks are sensitivity list incomplete. Vhdl is a strong type language, don't you get a error message about that when you compile the codes?
 

linuxluo

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Hi,
2 is error because the designer want to latch "z" state . it's illegal.
 

linuxluo

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Hi
4 is simulated in error because incomplete sensitive list but can be synthesis correctly and gate simulation correctly.
 

dennisplus

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please read the VHDL book carefully, all the sensitive list should include in the process. or you will get a error result.
 

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