scan synthesis? What's your mean?
If you want a netlist with test ready state?
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i want test ready compile and inset scan chain. There are many gate-clocking in my design, when i run my script , there are many violation when dc execute "check_test" command, and it fails inserting scan chain. In other words, it' diffcult for me to insert scan chain for multiple-clock design.
Looks like your clocks are not fully controllable with clock-gating. How was clock gating inserted? Was it by a tool like PowerCompiler or actually put into the rtl by designer?
PowerCompiler has an option to turn off clock gating during scan. If it is put in by the designer, then he must disable the clock gating with a scan mode or a test mode pin, otherwise the flip-flops with gated-clocks will not be scannable.
another method to multiple-clock chain is insert a latch between two clock domain. This method can fix some setup violation and hold violation, But it can't solve all thing.