who can give me Scripts for scan synthesis ?

[jinruan]

Hi, all
I have some probelm in write script for scan synthesis, who will give me a example script?
Thanks!

Please email me: jinruan@sourcecore.com

 

[AlexWan]

Hi, jinruan

You may find a ebook named "Advance ASIC Chip Synthesis" in this forum. Some examples are in this book, and comments.

Good Luck

 

[horzonbluz]

scan synthesis? What's your mean?
If you want a netlist with test ready state?

 

[jinruan]

scan synthesis? What's your mean?
If you want a netlist with test ready state?
~~~~~~~~~~~~~~~~~~~~~~~~~~
i want test ready compile and inset scan chain. There are many gate-clocking in my design, when i run my script , there are many violation when dc execute "check_test" command, and it fails inserting scan chain. In other words, it' diffcult for me to insert scan chain for multiple-clock design.

 

[quake]

I dont think you simply need synthesis script, but
DFT method, you can refer to the DFT topic nearby if you hope to do the scan chain

 

[jjww110]

please refer to the following link:
www.tcleda.org, some example script

 

[dr_dft]

Looks like your clocks are not fully controllable with clock-gating. How was clock gating inserted? Was it by a tool like PowerCompiler or actually put into the rtl by designer?
PowerCompiler has an option to turn off clock gating during scan. If it is put in by the designer, then he must disable the clock gating with a scan mode or a test mode pin, otherwise the flip-flops with gated-clocks will not be scannable.

 

[AlexWan]

Hi jinruan

You have to insert a scan-chain for each clock domain. And do a pin-mux in the top level of your design.

 

[Bigdot]

another method to multiple-clock chain is insert a latch between two clock domain. This method can fix some setup violation and hold violation, But it can't solve all thing.