Hi ,
The verification methodology to choose depends on the design problem at hand.
1 ] complex Algorithmic design
design can be in systemc/verilog/vhdl
you can build testbench in systemc to verify the algorithmic model
Once you verify the algoritm , convert it into RTL using some behavioral
synthesis tools. the converted RTL again can be verified with the same
systemc testbench you used to verify the behaviural algorimic model.
similarly you can use the same testbench for GLS as well.
2 ] complex sdigital signal processing design
the same methodology mentioned above can be used.
People also use MATLAB in this case
3 ] Other designs
We have various HVLS and methodologies available today.
vera is comletely transforming into systemverilog
specman e is going to be there for some more time.
If the design is new , then it is always preferable to use
systemverilog based verification methodology OVM, VMM
both methodologies are powerful and having good support.
Since both methodologies are using the core systemverilog
language we dont have the problem of language.
When you compare openvera and specman e, both are completely
different languages and the methodologies built on them were incompatible.
systemverilog solves that problem . people can build their own methodology
using core systemverilog language
Systemverilog is the future of verification.
BR
Amar