vlsichipdesigner
Full Member level 2
system verilog behavioral synthesis
hi designers,
request you to throw some light on the verification methodology to be used for a chip
* what is the best verification language to be used?
* what all i need to take care to best design my testbench and to be portable , scalable across chips so that i can re-use the maximum.
* how to verify 3rd party IP's
Your thoughts/insights to verification methodology is required.
my prayers,
learn chip design freely no charges at all!!!
chip design made easy
https://www.vlsichipdesign.com
hi designers,
request you to throw some light on the verification methodology to be used for a chip
* what is the best verification language to be used?
* what all i need to take care to best design my testbench and to be portable , scalable across chips so that i can re-use the maximum.
* how to verify 3rd party IP's
Your thoughts/insights to verification methodology is required.
my prayers,
learn chip design freely no charges at all!!!
chip design made easy
https://www.vlsichipdesign.com