Which Topology is Suitable for these OTA Specifications

[shady205]

Hello Friends..


I need to design an OTA (Fully Differential) with the Specifications

Gain> = 65dB
UGB>= 500MHz
Phase Margin >=65 Degrees
Power Supply Rails are 1.8V and 0V
Output Swing (Max.Min) = (1.3V , 0.5V)

And the Current through the Differential Input Transistors is .75 mA

And i need to use only SingleStage Only..!

Thanks in Advance.

 

[bastos4321]

I would suggest a folded cascode topology.

Bastos

 

[shady205]

I tried that i got a gain of 78.9dB with 340MHz UGB and 8Degrees of Phase margin..

So how should i compensate the OTA..?

Added after 1 minutes:

my design lacks in stability...

the load cap should compensate the OTA but for my design the system is completely unstable.

 

[yschuang]

Phase margin and GBW depend on the type of input pair, pmos or nmos.
If pmos is the input pair and nmos will be the cascode devices, which mean larger
ft due to larger gm/(2pi*Cgtot), then you can expect better phase margin and worse GBW due to smaller gm of pmos.

 

[shady205]

My differential pair is nmos..

how do i compensate the circuit..?

actually the load cap should provide compensation to the circuit..

so, what should i do to get proper gain GBW and PM..? is there any compensation circuit that could improve my circuit..?

 

[yschuang]

It is easy to achieve high speed OTA with nmos input pair and hard to get good PM. GBW=gm(nmos)/(2pi*CL) F2d=ft(PMOS) Try to increase the power of cascode devices or reduce the length of cascode devices. Sometimes need to take care of miiler effer in the input pair.