which style is better

[alpacinoliu]

I:
assign out = (sel)?a:b;

II:
always @(sel or a or b) begin
if (sel)
out = a;
else
out = b;
end

somebody tell me I ,However others tell me II;
which is better or same. why?

thanks in advance

 

[cevitamic]

You know that there two kinds of models in Verilog descriptions, one is called "behavioral model" and the other one is called "logical model". It's usually recommended to use "logical model" in designs. In my opinion, both of them are "behavioral model", that means how this functional is sythesized is not controlled by you, but depends on the synthesizing tool you use. So, I think both of them are OK, or both of them are not OK. It's not important, becasue they are the same, except that you have another choise -- a logical model, which tell the synnthesizer how to implement this logic explicitly.

 

[echo47]

Yes, both give the same results.
I use method #1 because it's compact.
Method #2 is good if work for a stuffy company that pays you for each line of code you write.

 

[alpacinoliu]

You know that there two kinds of models in Verilog descriptions, one is called "behavioral model" and the other one is called "logical model". It's usually recommended to use "logical model" in designs. In my opinion, both of them are "behavioral model", that means how this functional is sythesized is not controlled by you, but depends on the synthesizing tool you use. So, I think both of them are OK, or both of them are not OK. It's not important, becasue they are the same, except that you have another choise -- a logical model, which tell the synnthesizer how to implement this logic explicitly.

hi cevitamic
you can describe the function of codes above in the "logical model".
thank you

 

[nafaiz]

both gives the same result.....so y u want to write long statement for (II).....

 

[adap]

As said both give the same results. However the first model is prefered because no sensitivity list is used and you can avoid errors by forgetting to put signals in the list.
If the code is more complex with nested if statements then the second model is more readable and thus better to use.
I think in the second model the <= should be used and not the =

 

[jarodz]

It is not sequential circuit. It is natural to use "=", not "<=".

I use style I when the multi selection signals is one hot encoded. On the others, the style II is used.
But I use case statement instead of if-else.
It it the reason that case statement is no priority normally.

Regards,
Jarod

 

[Jackwang]

I suggest style II.
for this struture is easy to understand. and it accords with hardware implementation principle of logic circuits

 

[venu pradeepa]

hi,

see there r 3 models in verilog

data flow modelling
behavioural
structural


I st one what u have given is data flow
II nd one is behavioural

the result i.e the hardware of both style is same,
but most of the designers use behavioural modelling ( easy to understand , if u r not sure abt
internal design of a system use this modelling )
but for ur system i.e MUX I st type is good.

cheers,

venus

 

[manik_vivek_82]

Hi,
Don't you think more registers will be inferred in the behavioral style of modelling?

 

[eeeraghu]

if it is a combinational logic go for the above style else go for the procedural style.

 

[Kulprashant]

hi,
first one will give you minimised circuit while second one can give priority based structure.

with regards,
kul.

 

[wkong_zhu]

I use the 1st one. because the code is less.
The two method is synthesized into the same circuit.

 

[power-twq]

II is better, because II is more readable and easy to be understood.

I:
assign out = (sel)?a:b;

II:
always @(sel or a or b) begin
if (sel)
out = a;
else
out = b;
end

somebody tell me I ,However others tell me II;
which is better or same. why?

thanks in advance