asgg said:Hi, I'm designing a LDO circuit. In order to aquire a large output current(100mA), I make the W/L of pass element PMOS 6000/1. But when RL is large, i.e. the output current is very small (such as 1uA), the pass element PMOS cuts off or works in linear region.
So, which region of pass element PMOS should be? All in saturation (output current is 100mA and 1uA)?
Thanks!
asgg said:thank you all!
But on the contrary,
my simulations show PMOS pass transistor(M6) get into linear or cut off region when load current is very small (1uA) and saturation when load current is very large(100mA).
The vin is 3.3V and vout is 1.8V. the vin is constant, so the vds of PMOS is constant 1.5V. any problem in my circuit?
surianova said:asgg said:thank you all!
But on the contrary,
my simulations show PMOS pass transistor(M6) get into linear or cut off region when load current is very small (1uA) and saturation when load current is very large(100mA).
The vin is 3.3V and vout is 1.8V. the vin is constant, so the vds of PMOS is constant 1.5V. any problem in my circuit?
as current source from PMOS to the load only 1 uA.. the voltage at node A tend to go higher or Vsg of PMOS will go lower or might be cutoff. I think it will not go to linear region as Vsg go lower.
surianova said:asgg said:thank you all!
But on the contrary,
my simulations show PMOS pass transistor(M6) get into linear or cut off region when load current is very small (1uA) and saturation when load current is very large(100mA).
The vin is 3.3V and vout is 1.8V. the vin is constant, so the vds of PMOS is constant 1.5V. any problem in my circuit?
as current source from PMOS to the load only 1 uA.. the voltage at node A tend to go higher or Vsg of PMOS will go lower or might be cutoff. I think it will not go to linear region as Vsg go lower.
surianova said:surianova said:asgg said:thank you all!
But on the contrary,
my simulations show PMOS pass transistor(M6) get into linear or cut off region when load current is very small (1uA) and saturation when load current is very large(100mA).
The vin is 3.3V and vout is 1.8V. the vin is constant, so the vds of PMOS is constant 1.5V. any problem in my circuit?
as current source from PMOS to the load only 1 uA.. the voltage at node A tend to go higher or Vsg of PMOS will go lower or might be cutoff. I think it will not go to linear region as Vsg go lower.
find what is minimum current Iout that PMOS can source but still maintain in saturation.
then make the make R1 and R2 able to sink that Iout
Iout= 1.8/(R1+R2)
or u put a resistor from node B to gnd to sink current to make the voltage at node A go lower to maintain PMOS in saturation.
hope it help and let me know the result.
ambreesh said:Hi asgg,
If you are asking the region of operation of pass trnsistor without the information on supply voltage and your regulated voltage, no onw can give you a correct answer.
If you have 3.3V as input and you need 1.8V as output, it is possible to use a NMOS also as a pass transistor depends what are the backbias number for your NMOS. It could give you faster responce time.
Are you using .35u technology, if yes you could have lesser length for your pass transistor, minimum.
If you have 6000 as W/L ratio, to source only 1 uA of current the device has to be in cutoff. If you say it is in linear region then your Vds<vdsat or Vds<Vgs-vth, and that looks very odd to me. Rather I would request you to kindly revisit your design. It has to be in cutoff.
asgg said:Hi, I'm designing a LDO circuit. In order to aquire a large output current(100mA), I make the W/L of pass element PMOS 6000/1. But when RL is large, i.e. the output current is very small (such as 1uA), the pass element PMOS cuts off or works in linear region.
So, which region of pass element PMOS should be? All in saturation (output current is 100mA and 1uA)?
Thanks!
suria3 said:surianova said:surianova said:asgg said:thank you all!
But on the contrary,
my simulations show PMOS pass transistor(M6) get into linear or cut off region when load current is very small (1uA) and saturation when load current is very large(100mA).
The vin is 3.3V and vout is 1.8V. the vin is constant, so the vds of PMOS is constant 1.5V. any problem in my circuit?
as current source from PMOS to the load only 1 uA.. the voltage at node A tend to go higher or Vsg of PMOS will go lower or might be cutoff. I think it will not go to linear region as Vsg go lower.
find what is minimum current Iout that PMOS can source but still maintain in saturation.
then make the make R1 and R2 able to sink that Iout
Iout= 1.8/(R1+R2)
or u put a resistor from node B to gnd to sink current to make the voltage at node A go lower to maintain PMOS in saturation.
hope it help and let me know the result.
I agree with surianova's explanation. We should able to keep the pass MOS in saturation region for two main purposes, which are for LDO output voltage accuracy and for LDO loop stability.
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