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Which region of pass element(LDO) should be?

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asgg

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Hi, I'm designing a LDO circuit. In order to aquire a large output current(100mA), I make the W/L of pass element PMOS 6000/1. But when RL is large, i.e. the output current is very small (such as 1uA), the pass element PMOS cuts off or works in linear region.
So, which region of pass element PMOS should be? All in saturation (output current is 100mA and 1uA)?

Thanks!
 

jjsnail

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when the load is heavy,the pass element is in the linear region because the voltage of gate is very low

when the current get smaller ,the gate voltage will be higher and finally the pass element will get into saturation
 

czfaileen

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It is no need to keep pass transistor to be in sat region, in fact , real LDO means low drop out, that means the vds of pass transistor is very small, so it works in linear region in most time.
 

surianova

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asgg said:
Hi, I'm designing a LDO circuit. In order to aquire a large output current(100mA), I make the W/L of pass element PMOS 6000/1. But when RL is large, i.e. the output current is very small (such as 1uA), the pass element PMOS cuts off or works in linear region.
So, which region of pass element PMOS should be? All in saturation (output current is 100mA and 1uA)?

Thanks!
u can put a small resistor Rmin in parallel with the load.. so that the MOS will able to source some minumun current to Rmin and also 1uA to the load and enable the MOS in saturation all the time.
 

dhasmana

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If the PMOS pass transistor will come in linear region (high load current) , then the loop-gain will get screwed and hence load regulation will get screwed.How much it will get screwed depends upon the gain of the loop at the PMOS gate (loop gain excluding the PMOS stage gain).
 

asgg

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thank you all!
But on the contrary,
my simulations show PMOS pass transistor(M6) get into linear or cut off region when load current is very small (1uA) and saturation when load current is very large(100mA).
The vin is 3.3V and vout is 1.8V. the vin is constant, so the vds of PMOS is constant 1.5V. any problem in my circuit?
 

surianova

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asgg said:
thank you all!
But on the contrary,
my simulations show PMOS pass transistor(M6) get into linear or cut off region when load current is very small (1uA) and saturation when load current is very large(100mA).
The vin is 3.3V and vout is 1.8V. the vin is constant, so the vds of PMOS is constant 1.5V. any problem in my circuit?
as current source from PMOS to the load only 1 uA.. the voltage at node A tend to go higher or Vsg of PMOS will go lower or might be cutoff. I think it will not go to linear region as Vsg go lower.
 

    asgg

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asgg

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surianova said:
asgg said:
thank you all!
But on the contrary,
my simulations show PMOS pass transistor(M6) get into linear or cut off region when load current is very small (1uA) and saturation when load current is very large(100mA).
The vin is 3.3V and vout is 1.8V. the vin is constant, so the vds of PMOS is constant 1.5V. any problem in my circuit?
as current source from PMOS to the load only 1 uA.. the voltage at node A tend to go higher or Vsg of PMOS will go lower or might be cutoff. I think it will not go to linear region as Vsg go lower.
yeah,:D, you are right! It cutoffs! And when 1uA,the voltage of node A is very high(2.9V). So how to tackle this problem?
 

surianova

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surianova said:
asgg said:
thank you all!
But on the contrary,
my simulations show PMOS pass transistor(M6) get into linear or cut off region when load current is very small (1uA) and saturation when load current is very large(100mA).
The vin is 3.3V and vout is 1.8V. the vin is constant, so the vds of PMOS is constant 1.5V. any problem in my circuit?
as current source from PMOS to the load only 1 uA.. the voltage at node A tend to go higher or Vsg of PMOS will go lower or might be cutoff. I think it will not go to linear region as Vsg go lower.

find what is minimum current Iout that PMOS can source but still maintain in saturation.

then make the make R1 and R2 able to sink that Iout

Iout= 1.8/(R1+R2)

or u put a resistor from node B to gnd to sink current to make the voltage at node A go lower to maintain PMOS in saturation.

hope it help and let me know the result.
 

    asgg

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ambreesh

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Hi asgg,
If you are asking the region of operation of pass trnsistor without the information on supply voltage and your regulated voltage, no onw can give you a correct answer.
If you have 3.3V as input and you need 1.8V as output, it is possible to use a NMOS also as a pass transistor depends what are the backbias number for your NMOS. It could give you faster responce time.
Are you using .35u technology, if yes you could have lesser length for your pass transistor, minimum.
If you have 6000 as W/L ratio, to source only 1 uA of current the device has to be in cutoff. If you say it is in linear region then your Vds<vdsat or Vds<Vgs-vth, and that looks very odd to me. Rather I would request you to kindly revisit your design. It has to be in cutoff.
 

    asgg

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suria3

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surianova said:
surianova said:
asgg said:
thank you all!
But on the contrary,
my simulations show PMOS pass transistor(M6) get into linear or cut off region when load current is very small (1uA) and saturation when load current is very large(100mA).
The vin is 3.3V and vout is 1.8V. the vin is constant, so the vds of PMOS is constant 1.5V. any problem in my circuit?
as current source from PMOS to the load only 1 uA.. the voltage at node A tend to go higher or Vsg of PMOS will go lower or might be cutoff. I think it will not go to linear region as Vsg go lower.

find what is minimum current Iout that PMOS can source but still maintain in saturation.

then make the make R1 and R2 able to sink that Iout

Iout= 1.8/(R1+R2)

or u put a resistor from node B to gnd to sink current to make the voltage at node A go lower to maintain PMOS in saturation.

hope it help and let me know the result.

I agree with surianova's explanation. We should able to keep the pass MOS in saturation region for two main purposes, which are for LDO output voltage accuracy and for LDO loop stability.
 

asgg

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ambreesh said:
Hi asgg,
If you are asking the region of operation of pass trnsistor without the information on supply voltage and your regulated voltage, no onw can give you a correct answer.
If you have 3.3V as input and you need 1.8V as output, it is possible to use a NMOS also as a pass transistor depends what are the backbias number for your NMOS. It could give you faster responce time.
Are you using .35u technology, if yes you could have lesser length for your pass transistor, minimum.
If you have 6000 as W/L ratio, to source only 1 uA of current the device has to be in cutoff. If you say it is in linear region then your Vds<vdsat or Vds<Vgs-vth, and that looks very odd to me. Rather I would request you to kindly revisit your design. It has to be in cutoff.
I'm using .18 process, and as you say the PMOS is in cutoff region not in linear region.
thanks!
 

engronger

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if you use NMOS as a pass element, the problem would be disappeared
otherwise ,if you want your LDO can out put from 100mA to 1uA , certainly it will work at linear region when load is rather big


asgg said:
Hi, I'm designing a LDO circuit. In order to aquire a large output current(100mA), I make the W/L of pass element PMOS 6000/1. But when RL is large, i.e. the output current is very small (such as 1uA), the pass element PMOS cuts off or works in linear region.
So, which region of pass element PMOS should be? All in saturation (output current is 100mA and 1uA)?

Thanks!
 

lijianheng

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For low dropout, in heavy load, the pass element maybe in linear region. For high gain at pass element stage, it is in saturation region.
 

rock_zhu

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suria3 said:
surianova said:
surianova said:
asgg said:
thank you all!
But on the contrary,
my simulations show PMOS pass transistor(M6) get into linear or cut off region when load current is very small (1uA) and saturation when load current is very large(100mA).
The vin is 3.3V and vout is 1.8V. the vin is constant, so the vds of PMOS is constant 1.5V. any problem in my circuit?
as current source from PMOS to the load only 1 uA.. the voltage at node A tend to go higher or Vsg of PMOS will go lower or might be cutoff. I think it will not go to linear region as Vsg go lower.

find what is minimum current Iout that PMOS can source but still maintain in saturation.

then make the make R1 and R2 able to sink that Iout

Iout= 1.8/(R1+R2)

or u put a resistor from node B to gnd to sink current to make the voltage at node A go lower to maintain PMOS in saturation.

hope it help and let me know the result.

I agree with surianova's explanation. We should able to keep the pass MOS in saturation region for two main purposes, which are for LDO output voltage accuracy and for LDO loop stability.
hi, But it will waste current and size. why regulator operate on the condition of 1uA drive current? just power down it.
 

arghpok

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And why LDO ? you're droping-out 3.3-1.8 = 1.5V, that's too much, and as it has been said before, why to drive such a little current.

If you use an nmos pass transistor, then your circuit will be a typical linear regulator, and those work under a minimum drop out about 1.5 (just what you have), your power consumption will be the same, but you won't have the problems you're experiencing until now.

Again, I don't quite understand what kind of load you're wanting to source.
 

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