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Which one is good for performance - Packed Array or Unpacked Array

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Member level 5
Dec 31, 1999
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Hi All,

I have a performance related question here regarding packed array vs. unpacked array. I am trying to determine which one would give better performance in terms of simulation using one of the following simulators:
-- Synopsys VCS
-- Mentor Graphics Questa
-- Cadence IUS

Note, I don't have a concern about visibility or synthesizability with either usage. I have parameterized instances of a block, where sideband signals and standard buses of these instances are bundled in a set of arrays (i.e. logic [N-1:0] clk; logic [N-1:0][63:0] data, etc., where N is a number of instances). I tried using packed array (for no good reason, just wanted to started out with one), but there seems to be some performance degradation with this approach (vs. having independence interconnects -- i.e. separate wires for each instance of the block). Would unpacked array be better instead, of course performance wise? How does a simulator handle packed array vs. unpacked array vs. traditional sets of wires? Can anyone shed light on this?


First, unpacked arrays are more type-safe than packed arrays. If you have logic [7:0] clk1; and logic clk2; then make an incorrect assignment clk1 = clk2, you will not see any error. In Verilog, all packed typed are assignment compatible and will be padded or truncated to fit. But if you had declared clk1 as logic clk[7:0]; that assignment will an error.

The key difference in performance between packed and unpacked arrays depends on how you plan to access them. Packed arrays are usually optimized for access as a whole, as a vector. So you might see a penalty for individual bit access. One the other hand, if you mostly access a packed array by bits, the compiler might optimize by breaking the array into individual bits, and you might pay a penalty for a single access as a whole.

My suggestion is to use unpacked array dimensions unless you have a specific need to use a packed array dimension. You need to use a packed array to represent a group of bits as an integral value, i.e. a 32-bit number.
Thanks Dave for your suggestions.

Though, it is not my primary concern (as this is mainly used for DUT<->TB interconnects), I do agree with you on the first paragraph. Good to keep in mind.

The rest of your suggestion is appealing to my needs, and it does make sense. I also don't have a huge need for bit-selection of a vector (a packed array of signals), but I think I can workaround those limitations by different means wherever I need.

One addition question: Has there been any study done to show how performance differs?


Good to know. I was lazy and wanted a quick answer; I think I can produce my own numbers. :)

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