Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
It is usually quite clear the performance of busses: AHB is a 2-stage pipelined system and so is fatsre than non-pipelined APB. However, AHB's split transactions are a bit messy, so AXI (AMBA 3) does that a lot better. Or even multi-layer AHB. The PLB from Coreconnect slots between the two in terms of architectural efficiency, but then there is an area and interconnect complexity tradeoff between the increased bandwidth and so on.
Really, you want a bus that is JUST fast enough, becuase otherwise you are wasting resource. On the other hand, the extensive analysis required to make that tardeoff might cost more than the savings you can make from it. There are so many options. Since time-to-market and risk are such big factors these days, I would say that go with the bus that the majority of your IP uses. You can alwasy use more than one bus: I have seen systems with both PLB and AMBA, where the CPU subsystem and internal memory used PLB and the on-chip peripherals used AHB.
If u r going to opt for AMBA, there r three different kinds of them.
AHB for high speed
APB for low power
AXI Multi layer bus architectur for advanced performance, and moreover as Amba is more popular than any other buses, there would be good support from many and the interfaces to the devices on the bus are easily available.
Thanks
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.