Which model to use for bidirectional IO ESD analysis?

[raonukathoti]

Hai everyone,
i am designing bidirectional IO buffer, in this there are three stages like core logic, level converter, pre-buffer and final driver.
But the output node is again feedback to pre-buffer.
my question is that the size of final driver and pre-buffer are different so that there may be chance of damage of pre-buffer transistor if feed back from output driver.
To avoid this, we should do ESD analysis so that we can use either HBM, CDM or MM ESD models.
and also which model is used for bidirectional IO?
and how to do this analysis?
i hope you will reply as soon as possible
for more clarification see the attached file.
thanks

 

[Fom]

esd analysis

As I know there is no tool for ESD analysis. This task requires something like 3D simulator.

 

[ESDSolutions]

spice esd behaviour

Hi raonukathoti

I am not sure that I understand your question. Either you want to measure your chip. In that case you can ESD equipment such as a TLP system which can provide a Voltage-Current behaviour graph. Many companies and research institutes own such equipment. You can also outsource this work to different test labs.

However, if your intention is to simulate the ESD behavior of your circuits then you need something else. In that case, I have a few questions for you
- Why do you want to simulate ESD behavior?
- Is it because there is lack of trust in the foundry supplied ESD solutions?
According to experts in the field Spice simulation of ESD is not accurate enough yet. currently models supplied by the foundry do not include high current, fast transient behavior required for such simulations. Certainly snapback behavior if NMOS devices is not covered in most foundry models.

- What simulator do you plan to use?
I guess you plan to use SPICE. As mentioned above not many models include the behavior required for ESD relevant simulations.
Some people tend to use TCAD simulators in 3D simulation. But the TCAD mesh network and process calibration influence the results drastically. Actually, even with these kind of simulations it is time consuming to get it right. If you can't spend full-time on the simulator it may be hard to get any relevant results!

Depending on the answers I might provide further reference.
- Good material exists for RC-triggered BigFET simulations from the people of Freescale. Watch out though, these solutions are patented and cannot be copied without a proper license!
- several people have spend phD's on the study of TCAD simulation for ESD. I can look up some paper references if that is what you are looking for.

- What technology are you working on? Is it a CMOS from amajor foundry, a high voltage option, SOI, ...?

Additionaly: check out this forum post: