That depends on requirement spec:
- delay/timing spec
- power versus switching/activity
If you look at mviswa's comment - it is correct.
It states - if they are in lower level of hierarchy use M1 or M2 - for example - two instances of INV placed close by - you try not to go beyond first 2 metal layers - it will increase unwanted parasitic via-res in path.
Full custom shape based routers will also do the same.
INV placed very far from each other - in such cases - there will be buffers in between [of course that depends on required switching speed and power optimization (PDP) in the path as per spec]
Now, if two such INVs are part of other cell in hierarchy - that means higher level of hierarchy - you use some P&R tools and watch for routing obstructions inside cell - routers connecting cells might use higher metal layers.
Yes, true, sheet res will be low for M5, M6 - however you insert additional via-resistances to climb up to M6, also - you might encounter more Signal Integrity issues as your interconnect goes a long distance. What is the max number of metal layers used in the process? - in case M5, M6 is part of power rail - prefer to avoid those, otherwise climbing up n down to cross power rails - more RC delay in the path.