which metal should be used?

[dazzling_deepika]

Please answer this question as I am preparing for an interview

There are 2 inverters connected in series.Justify which metal layer(lower like M1 or M2) or higher(M5 or M6) would you use to connect them

 

[mviswa]

If 2 inverter are in lower level of hirarchy , then use m1 or m2 .
Higher metals are used to carry more current & voltages like power signals.

my suggestion is use only lower metals likw M1 oe M2

Please answer this question as I am preparing for an interview

There are 2 inverters connected in series.Justify which metal layer(lower like M1 or M2) or higher(M5 or M6) would you use to connect them

 

[manruru]

u have to use metal 1 or 2 , if u want to connect in metal 5,6.
the starting metal is M1. routing from S,D will have to start from M1 only..
Gate u will connect thru poly ,M1 contact.
after it is depend on the requirement. if they r carrying higher currents and u want to reduce the resistance then we go for higher metals thru metal jumps.
if not just just route thru M1 or M2.

hope this helps....suggestion r more welcome....

 

[dazzling_deepika]

but supposing 2 cases:

inverters are pretty close to each other.

inverters are very far from each other.

then each of these cases which metal should be used?would nt it be better to use M5or M6 if the inverters are very far from each other as M5 and M6 have less resistance?Rabaey kind of confused me when it said that for long distance wiring one should use M1.Plz clarify my doubts

This question was actually asked at an onsite interview at Intel Corp.

 

[sat]

That depends on requirement spec:
- delay/timing spec
- power versus switching/activity

If you look at mviswa's comment - it is correct.
It states - if they are in lower level of hierarchy use M1 or M2 - for example - two instances of INV placed close by - you try not to go beyond first 2 metal layers - it will increase unwanted parasitic via-res in path.

Full custom shape based routers will also do the same.

INV placed very far from each other - in such cases - there will be buffers in between [of course that depends on required switching speed and power optimization (PDP) in the path as per spec]
Now, if two such INVs are part of other cell in hierarchy - that means higher level of hierarchy - you use some P&R tools and watch for routing obstructions inside cell - routers connecting cells might use higher metal layers.

Yes, true, sheet res will be low for M5, M6 - however you insert additional via-resistances to climb up to M6, also - you might encounter more Signal Integrity issues as your interconnect goes a long distance. What is the max number of metal layers used in the process? - in case M5, M6 is part of power rail - prefer to avoid those, otherwise climbing up n down to cross power rails - more RC delay in the path.

 

[dazzling_deepika]

I am sorry but i do not understand what you mean by " in lower level of hierarchy "

 

[sat]

Well, I can use two INV cells inside a 4x1_MUX cell [assume there are other cells as well inside 4x1_MUX AND2x1 etc..].
I can use several 4x1_MUX to construct another big_MUX, I can use my big_MUX cell/block and some other blocks to construct my ZOZO_cell [just a name].. and so on - until I reach my top level.

The INV instances inside 4x1_MUX are connected in lower level of hierarchy.

Now, inside my ZOZO_cell, there are instances of INV as well - they are in the higher level of hierarchy.

Hope that explains.