Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronic Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Register Log in

which kind of pattern file should be used during post-simulation

Status
Not open for further replies.

Hvyikey

Newbie level 4
Joined
Sep 20, 2010
Messages
6
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,317
Hi,friends
I use tetramax to write out pattern file in two kinds, stil and v,that is write_patterns -f verilog_single_file or write_paterns -f stil . Now I want to verify whether the generated patterns are right or not and I simulate it by adding the verilog_single_file ,dut module ,library module and spf file to Modelsim. And these are my questions .
(1)Is there anything wrong with my idea ?
(2) what is the DPV testbench used for ? Is it use to verify the patterns ,too? What's the differnce between two ideas.
(3)When I use DPV testbench, which kind of pattern file should I use, -verilog_single_file or -stil.
Thanks .
 

Hvyikey

Newbie level 4
Joined
Sep 20, 2010
Messages
6
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,317
Someone give me a hand ,please.Thanks .
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Top