the nand has a lower logical effort...which means a smaller delay...
the logical effort is simply the ratio between the input capacitance of a gate to that of the reference inverter with the same driving strength
the reference inverter is the one having the same rise and fall times
so by taking an inverter with a P:N ratio of 2...whose logical effort is 1
and comparing that with a nand gate (comparing their input capacitances)
you'll have the logical effort of the nand gate as 4/3
since it has an input capacitance of 4 (nmos(1) + nmos(1)+ pmos(2))
while the inverter has an input capacitance of 3 (nmos(1)+ pmos(2))
so the nand gate needs 4/3 of the current needed by an inverter to drive the same load
for the nor gate, this value is 5/3 and so the nor is much slower than the nand