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Many years ago, in 1960 - 1970 most popular was NOR. Only DTL and RTL logic - in this technologic basis NOR implementn more simple, then NAND.
In multriemmiter TTL NAND most simple. This basis very popular in 1970-1980/
In CMOS not differerence, but tradition. Therefore - NAND
I too prefer Nand because nand occupies less space in die
If u calculate the logical effort of nand then u will get the value as 4/3 and for Nor it is 5/3 so nand is having lesser delay so thts y we using nand rather than nor
and if u consider the rise and fall times of nand and nor also..it will beless for nand thats the reason we prefer nand...
If u compare nand versus inverter which occupies leser space and has lesser delay u wil say inverter so similarly the same case applies for nand and nor also
the nand has a lower logical effort...which means a smaller delay...
the logical effort is simply the ratio between the input capacitance of a gate to that of the reference inverter with the same driving strength
the reference inverter is the one having the same rise and fall times
so by taking an inverter with a P:N ratio of 2...whose logical effort is 1
and comparing that with a nand gate (comparing their input capacitances)
you'll have the logical effort of the nand gate as 4/3
since it has an input capacitance of 4 (nmos(1) + nmos(1)+ pmos(2))
while the inverter has an input capacitance of 3 (nmos(1)+ pmos(2))
so the nand gate needs 4/3 of the current needed by an inverter to drive the same load
for the nor gate, this value is 5/3 and so the nor is much slower than the nand