niraj_m
Junior Member level 1
Hi ,
Could you pl anyone let me know the best method to extract the behavioral model (verilog)for analog components like PLL or any analog component . Usually we see for Simulation purpose we hand-code at abstract level . however these models are proven to manual error , and hence live with bug at system level .
Pl do let me know the EDA tools used to write model for analog components .
Thanks in advance !
Niraj
Could you pl anyone let me know the best method to extract the behavioral model (verilog)for analog components like PLL or any analog component . Usually we see for Simulation purpose we hand-code at abstract level . however these models are proven to manual error , and hence live with bug at system level .
Pl do let me know the EDA tools used to write model for analog components .
Thanks in advance !
Niraj