which EDA tools used to write behavioral models for -PLL ?

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niraj_m

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Hi ,

Could you pl anyone let me know the best method to extract the behavioral model (verilog)for analog components like PLL or any analog component . Usually we see for Simulation purpose we hand-code at abstract level . however these models are proven to manual error , and hence live with bug at system level .

Pl do let me know the EDA tools used to write model for analog components .

Thanks in advance !
Niraj
 

As you mention, you need to create your model manually and checks them very carefully.
As far I know, there is not EDA tool to extract an analog functionnality, to be modelize in C/vhdl/ve/sv or what you want.
 

Yes I want to have model out of analog block .
So in this case does all the behavioral model for analog blocks are hand coded ones
?

Thanks for your reply ,
 

why not try to use verilogA module in cadence simulator！
 

verilogA is just an other language usuable
 

:roll:
I mean you can write behavioral models for PLL with verilogA language, and simulate these models with EDA tool “Cadence Spectre” .
 

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