Which DC synthesis warnings can be ignored?

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engr

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I am using the DC for synthesis, when i am using the "check_design" command before compile,report showing lots of warnings, i am confused which warnings are really needed to be removed so that we can go for compile.
Thanks in advance
 

Re: synthesis

without looking into the warnings, its difficult to say which can be ignored. After synthesis, use formality to check if the synthesis has gone ok. Other thing is: the design should 'link' properly.
Let me know the exact warning message, and may be I will be able to help
Kr,
Avi
 

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    engr

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Re: synthesis

If you can attach the report of check_design command to the post we can give you some meaningful suggestions.
 

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    engr

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