Jul 10, 2014 #1 I irun2 Member level 2 Joined Jan 20, 2008 Messages 49 Helped 0 Reputation 0 Reaction score 0 Trophy points 1,286 Activity points 1,701 Hi all, Can any one tell me which constraints written out by DC, like set_clock_latency/ set_clock_transition/ set_clock_uncertainty, will affect the clock spec generation in CTS stage? The generated Clock.ctstch looks like below: AutoCTSRootPin clkgen_m/u6/Z Period 40ns MaxDelay 0.01ns # sdc driven default MinDelay 0ns # sdc driven default MaxSkew 1600ps # sdc driven default SinkMaxTran 200ps # sdc driven default BufMaxTran 200ps # sdc driven default
Hi all, Can any one tell me which constraints written out by DC, like set_clock_latency/ set_clock_transition/ set_clock_uncertainty, will affect the clock spec generation in CTS stage? The generated Clock.ctstch looks like below: AutoCTSRootPin clkgen_m/u6/Z Period 40ns MaxDelay 0.01ns # sdc driven default MinDelay 0ns # sdc driven default MaxSkew 1600ps # sdc driven default SinkMaxTran 200ps # sdc driven default BufMaxTran 200ps # sdc driven default