YOu can buy the relative product from sy*opsys or C*dence, they both offer good system level simulation tools. But they are expensive.<
Or you can write it by your own. To do this, yOu must have good knowledge of ITU-T standards . I wrote one in verilog and it worked well in our chip development .
If you are doing a SDH chip design. Writing such testbench is quite good for your design. In fact, you can see it as a critical part of your design.Nerver see it as a unrelative job.
Sorry. I'm new in the e-language . I attend one seminar last month .
They introduce some eVC for us . As i know there are a lot of network/telcom eVC , you may ask others for more information .