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YOu can buy the relative product from sy*opsys or C*dence, they both offer good system level simulation tools. But they are expensive.<
Or you can write it by your own. To do this, yOu must have good knowledge of ITU-T standards . I wrote one in verilog and it worked well in our chip development .
If you are doing a SDH chip design. Writing such testbench is quite good for your design. In fact, you can see it as a critical part of your design.Nerver see it as a unrelative job.