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where to get test bench with VHDL for SDH chip?

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Junior Member level 3
Feb 9, 2002
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sdh testbench

where to get test bench with VHDL for SDH chip?

i want oc-192's testbench too,

is there any tool that can generate a full frame ?

Syn0psys S/o/n/e/t S/D/H w/o/r/k/b/e/n/c/h is exactly what you're looking for.

You, the wise , plz tell me how to get it?

Write or buy it !

YOu can buy the relative product from sy*opsys or C*dence, they both offer good system level simulation tools. But they are expensive.:)<
Or you can write it by your own. To do this, yOu must have good knowledge of ITU-T standards . I wrote one in verilog and it worked well in our chip development .
If you are doing a SDH chip design. Writing such testbench is quite good for your design. In fact, you can see it as a critical part of your design.Nerver see it as a unrelative job.

Agree! Understand the ITU standards and write simple testbench using verilog or C.

could you share this testbech? Plz!!!

The other solution is to use the eVC ( virtual component) from specman elite . However you shold acustom to e-language 1st .

Hi Nobody,
Have you used eVCs from Verisity? are they easy to use?
Where to evaluate them?


Sorry. I'm new in the e-language . I attend one seminar last month .
They introduce some eVC for us . As i know there are a lot of network/telcom eVC , you may ask others for more information .

Where can download the eVC of verisity?
Is there demo version of eVC such as ethernet SDH,or SONET

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