Continue to Site

Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

where is HDL SubSystem in DSP builder

Status
Not open for further replies.

alienx

Junior Member level 2
Joined
Feb 16, 2010
Messages
21
Helped
0
Reputation
0
Reaction score
0
Trophy points
1,281
Activity points
1,424
Hi,

I am new to DSP builder and FPGA programming. I was following DSP builder example which was on implementing FIR filter using DSP builder in Simulink and generating VHDL to be implement in my cyclone 2 FPGA. I came across this block as was given in the example steps which was "HDL SubSystem block" but I can't seem to find this block in my DSP builder library... could someone tell me what is wrong... I even tried reinstalling DSP builder..

here is the tutorial that I have been using to design me FIR filter using simulink.... its on page 39 step 10 from adobe file....its on the 2nd section Implementing DSP design using FPGA....
here is the link [ScanDoc] (3).pdf - 4shared.com - partage de documents - télécharger
 

any one....?? :(
 

Here is something that may help you:

Create a Library Model File with the HDL Subsystem Block
Create a Model File for your custom block by performing the following
steps in the Simulink software:
1. Choose New > Library (File menu).
2. Choose Save (File menu).
3. Save the file, e.g, as MyLib.mdl.
4. Open the Simulink Library Browser.
5. Expand the DSP Builder library.
6. Expand the Altlab library.
7. Drag and drop the HDL Subsystem block into your model.
8. Click the text HDL Subsystem.
9. Rename the block as DelayFIFO.
10. Choose Save (File menu).
Source : **broken link removed**
 

@farhada

there is no HDL subsystem block in DSP builder 9.0 library, I tried everything its not there,,, :(
 

@farhada

there is no HDL subsystem block in DSP builder 9.0 library, I tried everything its not there,,, :(

I am sorry, but I no longer have the DSP Builder, but you may send this question to Altera's help desk. I am sure they will be able to help you easily.
 

Thanks for trying farhada :) hopefully someone else might have the solution.... Could someone sent me the VHDL code for adaptive filter or point me to a Simulink model of an adaptive filter.....
 

Status
Not open for further replies.

Part and Inventory Search

Welcome to EDABoard.com

Sponsor

Back
Top