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Yes. We, divided DRC as two types. one is timing DRC and other one is layout DRC. Timing DRC includes max transition and max_capacitance (max load) violations. Timing DRC can be analyzed wrto your design and techno lib values using STA tools like PT for sign off. Some times library characterization values also feed into timing sign off tolls instaed of techno lib values.
Where as layout DRC includes Internal layer checks,wide metal checks , layer-to-layer checks . Can any BE enginer explain about how these checks are done with design and technology and which tools are sign off for this(other than hercules)?.
It varies from design to design. At logic synthesis level, you dont need to apply any tight constraints for DRC synthesis.We usually ignore the DRC violations at DC level. Again it depends on design to design and company policies. We usually follow the charactized load values at STA signoff level. You need to discuss with your backend team..90% DRC will be fixed at BE flow unless its big culprit at DC level...
To know more details about Library charcterization , please look into cadence white paper on "Motivations and Methodolgy for nanometer Library charcterization" .
Design Rules Specs ( I believe you are refering layout sign-off) are usually defined by Foundries/Fabs and based on the process complexity ( which sub-micron category).
technology libraries is more on tech files which important for layer mappings, conversions, layers assigns for de factor GDSII, and so on.
Hercules, Calibre, Assura, Diva, Dracula, Tanner L-Edit, Quartz, etc... all can be sign-off tools for physical verification depends on which Vendor your company choose to collaborate with the foundries.
For standard cell based ASIC we design a number of basic primitives (like NAND,NOR, Inverter,Mux,etc). The layout and schematic design part of this is called Library Development.. For timing and power analysis you should have all the information regarding a particular cell (e.g, for given input slew and output load how much delay it should have and power also)..This part of the Library design procedure is called characterization, in which you calculate delay and power for each library primitive for given input slew and output capacitance range....
Library Characterization may also involve the recharacterization of existing designs when there are shifts in the process flow. Typically, fabs will update the spice models if the process shifts (as they do with time or new equipment or whatever -- especially if new process). So you will need to recharacterize the libraries, otherwise the simulations you do with the primitives would be misleading or out of date or inaccurate - take your pick.
DRC analyzes the geometries of your layout to see whether they correspond to the design rules set out by the fab. At one time, during micrometer age, complying with the design rules provided to you by the fab should give you statistically better yield. Then submicron came along with nanometer dimensions and you suddenly find that you need to follow stricter recommended rules to get relatively better yield. I imagine rules are getting more and more rigid now and recently people are talking about model based drc.