At what point should i be adding IO buffers? Is it part of the synthesis step? Do i need to manually add them in the verilog netlist or is this part of the synthesis step? Or is it done during layout?
If you have the lib files of IO buffer, just add it into link library and target library. After that, you can add IO buffer to your RTL code and synthesize it.
At what point should i be adding IO buffers? Is it part of the synthesis step? Do i need to manually add them in the verilog netlist or is this part of the synthesis step? Or is it done during layout?
You add the IO into your RTL in a serperate module. After you synthesized the whole log of your chip link the IO into your design. Then you sign off the whole GTL with IOs in it to the layout.
By such method in the layout stage you could find the IO easily. And LVS and STA could be done easily.
Here is another possible flow. If you are using JTAG boundary scan, some tools like Synopsys BSDCompiler and Mentor's BSDArchitect can insert both the boundary scan cells and the associated IO buffers in the design.
In our design, we don't let tools to select the IO type. you should inst. the IO type by yourself in the RTL top level. The partition should like this: rtl_core and rtl_pad.
you set the IO pad don't touch during the synthesis flow.
I prefer that IO pad block shall be separated from the other functional blocks to ease the resue!
Since the IP pad provided by some fab are less timing accurate, our company use the custermised ones to replace the IP pads provided in the fab's lib.
For a totally new system implementation, you first synthesize the design using the IO Pads provided in the lib with the contraints. Later, you can customerize them to better adpat to your design requirements.
In our design, we don't let tools to select the IO type. you should inst. the IO type by yourself in the RTL top level. The partition should like this: rtl_core and rtl_pad.
you set the IO pad don't touch during the synthesis flow.